1. Field of the Invention
The present invention relates to an apparatus and method of accessing a central processing unit (CPU) with a generic CPU processing unit, and more particularly, to a method for programmably configuring the CPU processing unit so that it may be used on a plurality of switching devices.
2. Description of the Related Art
A switching system may include one or more network devices, such as a switching chip, each of which includes several modules that are used to process information that is transmitted through the device. Specifically, the device includes an ingress module, a Memory Management Unit (MMU) and an egress module. The ingress module includes switching functionality for determining to which destination port a packet should be directed. The MMU is used for storing packet information and performing resource checks. The egress module is used for performing packet modification and for transmitting the packet to at least one appropriate destination port. One of the ports on the device may be a CPU port that enables the device to send and receive information to and from external switching/routing control entities or CPUs.
As packets enter the device from multiple ports, they are forwarded to the ingress module where switching is performed on the packets. Thereafter, the packets are transmitted to the MMU for further processing. Thereafter, the egress module transmits the packets to at least one destination port, possibly including a CPU port. If information is being transmitted to the CPU port, the egress module forwards the information through a CPU processing unit, such as a Central Processing Unit Management Interface Controller (CMIC™) module, which takes care of all CPU management functions. For example, the CMIC™ module takes care of sending and receiving packets to and from the CPU port, changing the register memory settings and interfacing with internal and/or external busses.
Even in a family of switching chips that share the same architecture, the number of ports and the speed supported by the ports, among other features, may vary. As such, each switching chip in a shared architecture family has a CMIC™ design that is customized for that switching chip depending on, for example, the number and speed of ports associated with the switching chip. Such customization in the CMIC™ module is expensive, time consuming and error-proned. Therefore, there is a need for a generic CMIC™ module that may be used in various switching chips that share a common architecture.